Phase lock loop (PLL) circuits are used in high-speed communication devices and electronic testing instruments to generate a continuous wave signal at a precise and stable frequency. Phase lock loop circuits generally include a reference frequency, a synthesizer and a voltage controlled oscillator (VCO). Two known synthesizers used in PLL circuits are the integer N synthesizer and fractional N synthesizer. Integer N synthesis utilizes whole integers to synthesize the reference frequency thus providing a coarser resolution than fractional N synthesis, which utilizes fractional levels for a finer resolution.
Reducing lock time in a PLL circuit is always of utmost importance in the design of high-speed communication devices. One technique for reducing lock time includes the use of a regular (speed) charge pump and a faster (speed) charge pump in a fractional N synthesizer to provide for speedier signal acquisition. Unfortunately, the use of two different charge pumps generates a transition, also referred to as a transition glitch, which can negatively impact lock time. Hence, there is a need to minimize or eliminate the transition glitch which will improve the fractional N phase lock loop performance.